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ftg for via? pentium 4? chipsets cy28325-3 rev 1.0, november 21, 2006 page 1 of 18 2200 laurelwood road, santa clara, ca 95054 tel:(4 08) 855-0555 fax:(408) 855-05 50 www.spectralinear.com features ? spread spectrum frequency timing generator for via pt/m 266-800 pentium ? 4 chipsets ? programmable clock output frequency with less than 1 mhz increment ? integrated fail-safe watchdog timer for system recovery ? selectable hardware or software-programmed clock frequency when watchdog timer time-out ? capable to generate syst em reset after a watchdog timer time-out occurs or a change in output frequency via smbus interface ? support smbus byte read/write and block read/write operations to simplify system bios development ? vendor id and revision id support ? programmable-drive strength support ? programmable-output skew support ? three copies agp clocks ? power management control inputs ? available in 48-pin ssop note: 1. pins marked with [*] have internal pull-up resistors. pins marked with[^] have internal pull-down resistors. cpu agp pci ref apic 48m 24_48m x 3 x 3 x 9 x 1 x 2 x 1 x 1 ~ block diagram pin configuration vdd_ref xtal pll ref freq x2 x1 vdd_pci osc sclk pll 1 smbus logic vdd_48mhz sdata vdd_agp divider network vdd_cpu (3.3v) stop clock control stop clock control pll2 *(fs0:4) 2 *cpu_stop# pd# *pci_stop# ssop-48 ref vtt_pwrgd# *fs4/ref vdd_ref gnd_ref x1 x2 vdd_48mhz *fs3/48mhz *fs2/24_48mhz gnd_48mhz *fs0/pci_f *fs1/pci1 *mult_sel1/pci2 gnd_pci pci3 pci4 vdd_pci pci5 pci6 pci7 gnd_pci pci8 *pd# agp0 vdd_agp 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 28 27 26 25 32 31 30 29 vdd_apic gnd_apic apic0 apic1 gnd_cpu vdd_cpu_cs(2.5v) cput_cs_f cpuc_cs_f cput_0 cpuc_0 vdd_cpu(3.3v) iref gnd_cpu cput_1 cpuc_1 vtt_pwrgd# cpu_stop#* pci_stop#* rst# sdata sclk agp2 agp1 gnd_agp cy28325-3 *multsel1 agp0:2 pci_f pci1:8 48mhz 24_48mhz rst# vdd_apic apic0:1 cput_cs, cpuc_cs vdd_cpu_cs (2.5v) cput_0,1, cpuc_0,1 [1]
cy28325-3 rev 1.0, november 21, 2006 page 2 of 18 pin definitions pin name no. type description x1 4 i crystal connection or external reference frequency input: this pin has dual functions. it can be used as an external 14.318-mhz crystal con- nection or as an external reference frequency input. x2 5 o crystal connection: connection for an external 14.318-mhz crystal. if using an external reference, this pin must be left unconnected. ref/fs4 1 i/o reference clock output/frequency select 4: 3.3v 14.318-mhz output. this pin also serves as a power-on strap option to determine device oper- ating frequency as described in the frequency selection table. cput_0:1 cpuc_0:1 40, 39, 35, 34 o cpu clock outputs: frequency is set by the fs0:4 inputs or through serial input interface. cput_cs_f cpuc_cs_f 42, 41 o cpu clock outputs for chipset: frequency is set by the fs0:4 inputs or through serial input interface. apic0:1 46, 45 o apic clock output: apic clock outputs running at half of pci output frequency. agp 0:2 23, 26, 27 o agp clock output: 3.3v agp clock. pci_f/fs0 10 i/o free-running pci output 1/frequency select 1: 3.3v free-running pci output. this pin also serves as a power-on strap option to determine device operating frequency as described in the frequency selection table. pci1/fs1 11 i/o pci output 1 /frequency select 1: 3.3v pci output. this pin also serves as a power-on strap option to dete rmine device operating frequency as described in the frequency selection table. pci2/multsel1 12 i/o pci output 2/current multiplier selection 1: 3.3v pci output. this pin also serves as a power-on strap option to determine the current multiplier for the cpu clock outputs. the multsel definitions are as follows: multisel 0 = ioh is 4 iref 1 = ioh is 6 iref pci3:8 14, 15, 17, 18, 19, 21 o pci clock output 3 to 8: 3.3v pci clock outputs. 48mhz/fs3 7 i/o 48-mhz output/frequency select 3: 3.3v fixed 48-mhz, non-spread spectrum output. this pin also serves as a power-on strap option to deter- mine device operating frequency as de scribed in the frequency selection ta b l e . 24_48mhz/fs2 8 i/o 24- or 48-mhz output/frequency select 2: 3.3v fixed 24- or 48-mhz non-spread spectrum output. this pi n also serves as a power-on strap option to determine device operating frequency as described in the fre- quency selection table. cpu_stop# 32 i cpu output control: 3.3v lvttl-compatible input that disables cput_cs, cpuc_cs, cput_0:1 and cpuc_0:1. pci_st0p# 31 i pci output control: 3.3v lvttl-compatible input that disables pci1:8. pd# 22 i power-down control: 3.3v lvttl-compatible input that places the device in power down mode when held low. sclk 28 i smbus clock input: clock pin for serial interface. sdata 29 i/o smbus data input: data pin for serial interface. rst# 30 o (open-drain) system reset output: open-drain system reset output. iref 37 i current reference for cpu output: a precision resistor is attached to this pin, which is connected to the internal current reference.
cy28325-3 rev 1.0, november 21, 2006 page 3 of 18 vtt_pwrgd# 33 i power-good from voltage regulator module (vrm): 3.3v lvttl input. vtt_pwrgd# is a level sensitive str obe used to determine when fs0:4 and multsel inputs are valid and ok to be sampled (active low). once vtt_pwrgd# is sampled low, the st atus of this input will be ignored. vdd_cpu_cs, vdd_apic 43, 48 p 2.5v power connection: power supply for cpu_cs outputs buffers and apic output buffers. connect to 2.5v. vdd_ref, vdd_48mhz, vdd _pci, vdd_agp, vdd_cpu 2, 6, 16, 24, 38 p 3.3v power connection: power supply for cpu outputs buffers, 3v66 output buffers, pci output buffers, reference output buffers and 48-mhz output buffers. connect to 3.3v. gnd_ref gnd_48mhz, gnd_pci, gnd_agp, gnd_cpu, gnd_apic 3, 9, 13, 20, 25, 36, 44, 47 g ground connection: connect all ground pi ns to the common system ground plane. table 1. frequency selection table input conditions output frequency pll gear constants (g) fs4 fs3 fs2 fs1 fs0 cpu agp pci apic sel4 sel3 sel2 sel1 sel0 0 0 0 0 0 102.0 68.0 34.0 17.0 48.00741 0 0 0 0 1 105.0 70.0 35.0 17.5 48.00741 0 0 0 1 0 108.0 72.0 36.0 18.0 48.00741 0 0 0 1 1 111.0 74.0 37.0 18.5 48.00741 0 0 1 0 0 114.0 76.0 38.0 19.0 48.00741 0 0 1 0 1 117.0 78.0 39.0 19.5 48.00741 0 0 1 1 0 120.0 80.0 40.0 20.0 48.00741 0 0 1 1 1 123.0 82.0 41.0 20.5 48.00741 0 1 0 0 0 126.0 63.0 31.5 18.0 48.00741 0 1 0 0 1 130.0 65.0 32.5 18.5 48.00741 0 1 0 1 0 136.0 68.0 34.0 17.0 48.00741 0 1 0 1 1 140.0 70.0 35.0 17.5 48.00741 0 1 1 0 0 144.0 72.0 36.0 18.0 48.00741 0 1 1 0 1 148.0 74.0 37.0 18.5 48.00741 0 1 1 1 0 152.0 76.0 38.0 19.0 48.00741 0 1 1 1 1 156.0 78.0 39.0 19.5 48.00741 1 0 0 0 0 160.0 80.0 40.0 20.0 48.00741 1 0 0 0 1 164.0 82.0 41.0 20.5 48.00741 1 0 0 1 0 166.6 66.6 33.3 16.7 48.00741 1 0 0 1 1 170.0 68.0 34.0 17.0 48.00741 1 0 1 0 0 175.0 70.0 35.0 17.5 48.00741 1 0 1 0 1 180.0 72.0 36.0 18.0 48.00741 pin definitions (continued) pin name no. type description
cy28325-3 rev 1.0, november 21, 2006 page 4 of 18 1 0 1 1 0 185.0 74.0 37.0 18.5 48.00741 1 0 1 1 1 190.0 76.0 38.0 19.0 48.00741 1 1 0 0 0 100.9 67.3 33.6 16.8 48.00741 1 1 0 0 1 133.9 67.0 33.5 16.7 48.00741 1 1 0 1 0 200.5 66.8 33.4 16.7 48.00741 1 1 0 1 1 166.8 66.7 33.3 16.7 48.00741 1 1 1 0 0 100.0 66.6 33.3 16.7 48.00741 1 1 1 0 1 133.3 66.6 33.3 16.7 48.00741 1 1 1 1 0 200.0 66.6 33.3 16.7 48.00741 1 1 1 1 1 166.7 66.7 33.3 16.7 48.00741 table 1. frequency selection table (continued) input conditions output frequency pll gear constants (g) fs4 fs3 fs2 fs1 fs0 cpu agp pci apic sel4 sel3 sel2 sel1 sel0 swing select functions multsel1 multsel0 board target trace/term z reference r, iref = vdd/(3*rr) output current v oh @ z 00 50 rr = 221 1%, iref = 5.00 ma i oh = 4*iref 1.0v @ 50 00 60 rr = 221 1%, iref = 5.00 i oh = 4*iref 1.2v @ 60 01 50 rr = 221 1%, iref = 5.00 ma i oh = 5*iref 1.25v @ 50 01 60 rr = 221 1%, iref = 5.00 ma i oh = 5*iref 1.5v @ 60 10 50 rr = 221 1%, iref = 5.00 ma i oh = 6*iref 1.5v @ 50 10 60 rr = 221 1%, iref = 5.00 ma i oh = 6*iref 1.8v @ 60 11 50 rr = 221 1%, iref = 5.00 ma i oh = 7*iref 1.75v @ 50 11 60 rr = 221 1%, iref = 5.00 ma i oh = 7*iref 2.1v @ 60 00 50 rr = 475 1%, iref = 2.32 ma i oh = 4*iref 0.47v @ 50 00 60 rr = 475 1%, iref = 2.32 ma i oh = 4*iref 0.56v @ 60 01 50 rr = 475 1%, iref = 2.32 ma i oh = 5*iref 0.58v @ 50 01 60 rr = 475 1%, iref = 2.32 ma i oh = 5*iref 0.7v @ 60 10 50 rr = 475 1%, iref = 2.32 ma i oh = 6*iref 0.7v @ 50 10 60 rr = 475 1%, iref = 2.32 ma i oh = 6*iref 0.84v @ 60 1 1 50 ohm rr = 475 1%, iref = 2.32ma i oh = 7*iref 0.81v @ 50 1 1 60 ohm rr = 475 1%, iref = 2.32ma i oh = 7*iref 0.97v @ 60
cy28325-3 rev 1.0, november 21, 2006 page 5 of 18 serial data interface to enhance the flexibility and functi on of the clock synthesizer, a two-signal serial interface is provided. through the serial data interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. the registers associated with the serial data interface initial- izes to their default setting upon power-up, and therefore use of this interface is optional. clock device register changes are normally made upon syst em initialization, if any are required. the interface cannot be used during system operation for pow- er management functions. data protocol the clock driver serial protocol accepts byte write, byte read, block write, and block read opera tions from the controller. for block write/read operation, the by tes must be accessed in se- quential order from lowest to hi ghest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. for byte write and byte read operations, the sys- tem controller can access individually indexed bytes. the off- set of the indexed byte is encoded in the command code, as described in table 2 . the block write and block read protocol is outlined in table 3 while table 4 outlines the corresponding byte write and byte read protocol. the slave rece iver address is 11010010 (d2h). t table 2. command code definition bit description 7 0 = block read or block write operation, 1 = byte read or byte write operation (6:0) byte offset for byte read or byte write operation. fo r block read or block write operations, these bits should be '0000000' table 3. block read and block write protocol block write protocol block read protocol bit description bit description 1 start 1 start 2:8 slave address ? 7 bits 2:8 slave address ? 7 bits 9 write = 0 9 write = 0 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8 bit '00000000' stands for block operation 11:18 command code ? 8 bit '00000000' stands for block operation 19 acknowledge from slave 19 acknowledge from slave 20:27 byte count ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29:36 data byte 1 ? 8 bits 28 read = 1 37 acknowledge from slave 29 acknowledge from slave 38:45 data byte 2 ? 8 bits 30:37 byte count from slave ? 8 bits 46 acknowledge from slave 38 acknowledge from master .... ...................... 39:46 data byte from slave ? 8 bits .... data byte (n?1) ?8 bits 47 acknowledge from master .... acknowledge from slave 48:55 data byte from slave ? 8 bits .... data byte n ?8 bits 56 acknowledge from master .... acknowledge from slave .... data byte n from slave ? 8 bits .... stop .... acknowledge from master .... stop
cy28325-3 rev 1.0, november 21, 2006 page 6 of 18 table 4. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1start 1start 2:8 slave address ? 7 bits 2:8 slave address ? 7 bits 9 write = 0 9 write = 0 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8 bits '100xxxxx' stands for byte operation, bits[4:0] of the command code represents the offset of the byte to be accessed 11:18 command code ? 8 bits '100xxxxx' stands for byte operation, bits[4:0] of the command code represents the offset of the byte to be accessed 19 acknowledge from slave 19 acknowledge from slave 20:27 data byte from master ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29 stop 28 read = 1 29 acknowledge from slave 30:37 data byte from slave ? 8 bits 38 acknowledge from master 39 stop
cy28325-3 rev 1.0, november 21, 2006 page 7 of 18 data byte configuration map data byte 0 bit pin# name description power-on default 7 ? reserved reserved 0 6 ? sel2 sw frequency selection bits. refer to frequency selection table 0 5 ? sel1 sw frequency selection bits. refer to frequency selection table 0 4 ? sel0 sw frequency selection bits. refer to frequency selection table 0 3 ? fs_override 0 = select operating frequency by fs[4:0] input pins 1 = select operating frequency by sel[4:0] settings 0 2 ? sel4 sw frequency selection bits. refer to frequency selection table 0 1 ? sel3 sw frequency selection bits. refer to frequency selection table 0 0 ? reserved reserved 0 data byte 1 bit pin# name description power-on default 7 ? reserved reserved 0 6 ? spread select2 ?000? = off ?001? = reserved ?010? = reserved ?011? = reserved ?100? = 0.25% ?101? = ? 0.5% ?110?= 0.5% ?111? = 0.38% 0 5 ? spread select1 0 4 ? spread select0 0 3 42, 41 cput_cs, cpuc_cs (active/inactive) 1 2 35, 34 cput_1, cpuc_1 (active/inactive) 1 1 40, 39 cput_0, cpuc_0 (active/inactive) 1 0 ? cpu_cs_f stop control 1 = cput_cs_f and cpuc_cs_f are free-running outputs 0 = cput_cs_f and cpuc_cs_f will be disabled when cpu_stop# is active 1 data byte 2 bit pin# name pin description power-on default 7 21 pci8 1 = enabled, 0 = disabled 1 6 19 pci7 1 = enabled, 0 = disabled 1 5 18 pci6 1 = enabled, 0 = disabled 1 4 17 pci5 1 = enabled, 0 = disabled 1 3 15 pci4 1 = enabled, 0 = disabled 1 2 14 pci3 1 = enabled, 0 = disabled 1 1 12 pci2 1 = enabled, 0 = disabled 1 0 11 pci1 1 = enabled, 0 = disabled 1 data byte 3 bit pin# name pin description power-on default 7 ? reserved reserved 0
cy28325-3 rev 1.0, november 21, 2006 page 8 of 18 6 8 sel_48mhz 0 = 24 mhz 1 = 48 mhz 0 5 7 48mhz 1 = enabled, 0 = disabled 1 4 8 24_48mhz 1 = enabled, 0 = disabled 1 3 10 pci_f 1 = enabled, 0 = disabled 1 2 27 agp2 1 = enabled, 0 = disabled 1 1 26 agp1 1 = enabled, 0 = disabled 1 0 23 agp0 1 = enabled, 0 = disabled 1 data byte 4 bit pin# name pin description power-on default 7 ? pci_skew1 pci skew control 00 = normal 01 = ?500 ps 10 = reserved 11 = +500 ps 0 6 ? pci_skew0 0 5 ? wd_timer4 these bits store the time-out value of the watchdog timer. the scale of the timer is determine by the prescaler. the timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. if the prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. when the watchdog timer reaches ?0,? it will set the wd_to_status bit and generate reset if rst_en_wd is enabled. 1 4 ? wd_timer3 1 3 ? wd_timer2 1 2 ? wd_timer1 1 1 ? wd_timer0 1 0 ? wd_pre_scaler 0 = 150 ms 1 = 2.5 sec 0 data byte 5 bit pin# name pin description power-on default 7 7 48mhz_drv 48-mhz clo ck output drive strength 0 = normal 1 = high drive 1 6 8 24_48mhz_drv 24_48 mhz clock output drive strength 0 = normal 1 = high drive 1 5 45 apci1 (active/inactive) 1 4 46 apic0 (active/inactive) 1 3 ? sw_multsel1 iref multiplier 00 = ioh is 4 iref 01 = ioh is 5 iref 10 = ioh is 6 iref 11 = ioh is 7 iref 0 2 ? sw_multsel0 0 1 1 ref (active/inactive) 1 0 ? multsel_override this bit control the selection of iref multipler. 0 = hw control; iref multiplier is determined by multsel1 input pin 1 = sw control; iref multiplier is determined by sw_multsel[0:1] 0 data byte 6 bit pin# name pin description power-on default 7 ? reserved reserved 1 6 ? reserved reserved 1 data byte 3 bit pin# name pin description power-on default
cy28325-3 rev 1.0, november 21, 2006 page 9 of 18 5 ? reserved reserved 1 4 ? reserved reserved 1 3 ? reserved reserved 1 2 ? reserved reserved 1 1 ? reserved reserved 1 0 ? reserved reserved 1 data byte 7 bit pin# name pin description power-on default 7 ? reserved reserved 1 6 ? reserved reserved 1 5 ? reserved reserved 1 4 ? reserved reserved 1 3 ? reserved reserved 1 2 ? reserved reserved 1 1 ? reserved reserved 1 0 ? reserved reserved 1 data byte 8 bit pin# name pin description power-on default 7 ? revision_id3 revision id bit[3] 0 6 ? revision_id2 revision id bit[2] 0 5 ? revision_id1 revision id bit[1] 0 4 ? revision_id0 revision id bit[0] 0 3 ? vendor_id3 bit[3] of cypress?s vendor id. this bit is read-only. 1 2 ? vendor_id2 bit[2] of cypress?s vendor id. this bit is read-only. 0 1 ? vendor _id1 bit[1] of cypress?s vendor id. this bit is read-only. 0 0 ? vendor _id0 bit[0] of cypress?s vendor id. this bit is read-only. 0 data byte 9 bit pin# name pin description power-on default 7 ? reserved reserved 0 6 ? pci_drv pci clock output drive strength 0 = low drive 1 = high drive 0 5 ? agp_drv agp clock output drive strength 0 = low drive 1 = high drive 0 4 ? rst_en_wd this bit will enable the generation of a reset pulse when a watchdog timer time-out occurs. 0 = disabled 1 = enabled 0 3 ? rst_en_fc this bit will enable the generation of a reset pulse after a frequency change occurs. 0 = disabled 1 = enabled 0 data byte 6 (continued) bit pin# name pin description power-on default
cy28325-3 rev 1.0, november 21, 2006 page 10 of 18 2 ? wd_to_stat us watchdog timer time-out status bit 0 = no time-out occurs (read); ignore (write) 1 = time-out occurred (read); clear wd_to_status (write) 0 1 ? wd_en 0 = stop and re-load watchdog timer 1 = enable watchdog timer. it will start counting down after a frequency change occurs. note: cy28325-3 will generate system reset, re-load a recovery frequency, and lock itself into a recovery frequency mode after a watchdog timer time-out occurs. under recovery frequency mode, cy28325-2 will not respond to any attempt to change the output frequency via the smbus control bytes. system software can unlock the cy28325-3 from its recovery frequency mode by clearing the wd_en bit. 0 0 ? reserved reserved 0 data byte 10 bit pin# name pin description power-on default 7 ? cpu_cs_f skew2 cpu_cs_f skew control 000 = normal 001 = ?150 ps 010 = ?300 ps 011 = ?450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps 0 6 ? cpu_cs_f skew1 0 5 ? cpu_cs_f skew0 0 4 ? cpu_skew2 cput_0:1 and cpuc_0:1 skew control 000 = normal 001 = ?150 ps 010 = ?300 ps 011 = ?450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps 0 3 ? cpu_skew1 0 2 ? cpu_skew0 0 1 ? agp_skew1 agp skew control 00 = normal 01 = ?150 ps 10 = +150 ps 11 = +300 ps 0 0 ? agp_skew0 0 data byte 11 bit pin# name pin description power-on default 7 ? rocv_freq_n7 if rocv_freq_sel is set, the values programmed in rocv_freq_n[7:0] and rocv_f req_m[6:0] will be used to determine the recovery cpu output frequency when a watchdog timer time-out occurs. the setting of fs_override bit determines the frequency ratio for cpu and other output clocks. when fs_override bit is cleared, the same frequency ratio stated in the latched fs[4:0] register will be used. when it is set, the frequency ratio stated in the sel[4:0] register will be used. 0 6 ? rocv_freq_n6 0 5 ? rocv_freq_n5 0 4 ? rocv_freq_n4 0 3 ? rocv_freq_n3 0 2 ? rocv_freq_n2 0 1 ? rocv_freq_n1 0 0 ? rocv_freq_n0 0 data byte 9 (continued) bit pin# name pin description power-on default
cy28325-3 rev 1.0, november 21, 2006 page 11 of 18 data byte 12 bit pin# name pin description power-on default 7 ? rocv_freq_sel rocv_freq_sel determines the source of the recover frequency when a watchdog timer time-out occurs. th e clock generator will automatically switch to the recovery cpu fr equency based on the selection on rocv_freq_sel. 0 = from latched fs[4:0] 1 = from the settings of rocv _freq_n[7:0] & rocv_freq_m[6:0] 0 6 ? rocv_freq_m6 if rocv_freq_sel is set, the values programmed in rocv_freq_n[7:0] and rocv_freq_m[ 6:0] will be use to determine the recovery cpu output frequency when a watchdog timer time-out occurs. the setting of the fs_override bit determines the frequency ratio for cpu and other output clocks. when fs_override bit is cleared, the same frequency ratio stated in the latched fs[4:0] register will be used. when it is set, the frequency ratio stated in the sel[4:0] register will be used. 0 5 ? rocv_freq_m5 0 4 ? rocv_freq_m4 0 3 ? rocv_freq_m3 0 2 ? rocv_freq_m2 0 1 ? rocv_freq_m1 0 0 ? rocv_freq_m0 0 data byte 13 bit pin# name pin description power-on default 7 ? cpu_fsel_n7 if prog_freq_en is set, the values programmed in cpu_fsel_n[7:0] and cpu_fsel_m[6:0] will be used to det ermine the cpu output frequency. the new frequency will start to load w henever cpu_fselm[6:0] is updated. the setting of the fs_override bit det ermines the frequency ratio for cpu and other output clocks. when it is cleared, the same frequency ratio stated in the latched fs[4:0] register will be used. when it is set, the frequency ratio stated in the sel[4:0] register will be used. 0 6 ? cpu_fsel_n6 0 5 ? cpu_fsel_n5 0 4 ? cpu_fsel_n4 0 3 ? cpu_fsel_n3 0 2 ? cpu_fsel_n2 0 1 ? cpu_fsel_n1 0 0 ? cpu_fsel_n0 0 data byte 14 bit pin# name pin description power-on default 7 ? pro_freq_en programmable output frequencies enabled 0 = disabled 1 = enabled 0 6 ? cpu_fsel_m6 if prog_freq_en is set, the values programmed in cpu_fsel_n[7:0] and cpu_fsel_m[6:0] will be used to determine the cpu output fr equency. the new frequency will start to load whenever cpu_fselm[6:0] is updated. the setting of fs_override bit determines the frequency ratio for cpu and other output clocks. when it is cleared, the same frequency ratio stated in the latched fs[4:0] register will be used. when it is set, the frequency ratio stated in the sel[4:0] register will be used. 0 5 ? cpu_fsel_m5 0 4 ? cpu_fsel_m4 0 3 ? cpu_fsel_m3 0 2 ? cpu_fsel_m2 0 1 ? cpu_fsel_m1 0 0 ? cpu_fsel_m0 0 data byte 15 bit pin# name pin description power-on default 7 1 latched fs4 input latched fs[4:0] inputs. these bits are read-only. x 6 7 latched fs3 input x 5 8 latched fs2 input x 4 11 latched fs1 input x 3 10 latched fs0 input x
cy28325-3 rev 1.0, november 21, 2006 page 12 of 18 programmable output frequency, watchdog timer and recovery output frequency functional description the programmable output frequency feature allows users to generate any cpu out put frequency from the range of 50 mhz to 248 mhz. cypress offers the most dynamic and the simplest programming interface for system developers to utilize this feature in their platforms. the watchdog timer and recovery output frequency features allow users to implement a recovery mechanism when the system hangs or getting unstable. system bios or other control software can enable the watchdog timer before they attempt to make a frequ ency change. if the system hangs and a watchdog timer time-out occurs, a system reset will be generated and a recovery frequen cy will be activated. all the related registers are summarized in the following table. 2 ? reserved reserved 0 1 ? vendor test mode reserved. set = 1 1 0 ? vendor test mode reserved. set = 1 1 data byte 16 bit pin# name pin description power-on default 7 ? reserved reserved 0 6 ? reserved reserved 0 5 ? reserved reserved 0 4 ? reserved reserved 0 3 ? reserved reserved 0 2 ? reserved reserved 0 1 ? reserved reserved 0 0 ? reserved reserved 0 data byte 17 bit pin# name pin description power-on default 7 ? reserved reserved 0 6 ? reserved reserved 0 5 ? reserved reserved 0 4 ? reserved reserved 0 3 ? reserved reserved 0 2 ? reserved reserved 0 1 ? reserved reserved 0 0 ? reserved reserved 0 data byte 15 bit pin# name pin description power-on default table 5. register summary . name description pro_freq_en programmable output frequencies enabled 0 = disabled (default). 1 = enabled. when it is disabled, the operating output frequency will be determined by either the latched value of fs[4:0] inputs or the programmed value of sel[4:0]. if fs_override bit is clear, latched fs[4:0] inputs will be used. if fs_override bit is set, programmed value of sel[4:0] will be used. when it is enabled, the cpu output frequency will be determined by the programmed value of cpufsel_n, cpufsel_m and the pll gear constant. the program value of fs _override, sel[4:0] or the latched value of fs[4:0] will determine the pll gear constant and the frequency ratio between cpu and other frequency outputs.
cy28325-3 rev 1.0, november 21, 2006 page 13 of 18 program the cpu output frequency when the programmable output frequency feature is enabled (pro_freq_en bit is set), the cpu output frequency is deter- mined by the following equation: fcpu = g * (n+3)/(m+3). ?n? and ?m? are the values programmed in programmable frequency select n-value register and m-value register, respectively. ?g? stands for the pll gear constant, which is determined by the programmed value of fs[4:0] or sel[4:0]. the value is listed in table 6 . the ratio of (n+3) and (m+3) need to be greater than ?1? [(n+3)/(m+3) > 1]. the following table lists set of n and m values for different frequency output ranges.this example use a fixed value for the m-value register and select the cpu output frequency by changing the value of the n-value register. fs_override when pro_freq_en is cleared or disabled 0 = select operating frequency by fs input pins (default). 1 = select operating frequency by sel bits in smbus control bytes. when pro_freq_en is set or enabled 0 = frequency output ratio between cpu and other frequency groups and the pll gear constant are based on the latched value of fs input pins (default). 1 = frequency output ratio between cpu and other frequency groups and the pll gear constant are based on the programmed value of sel bits in smbus control bytes. cpu_fsel_n, cpu_fsel_m when prog_freq_en is set or enabled, the va lues programmed in cpu_fsel_n[7:0] and cpu_fsel_m[6:0] determines the cpu output frequency. the new frequency will start to load whenever there is an update to either cpu_fsel_n[7:0 ] or cpu_fsel_m[6:0]. th erefore, it is recom- mended to use word or block write to update bot h registers within the same smbus bus operation. the setting of fs_override bit determines the frequency ratio for cpu, agp and pic. when fs_override is cleared or disabled, the frequency ra tio follows the latched value of the fs input pins. when fs_override is set or enabled, the frequency ra tio follows the programmed value of sel bits in smbus control bytes. rocv_freq_sel rocv_freq_sel determines the source of the recover frequency when a watchdog timer time-out occurs. the clock generator will automatically swit ch to the recovery cpu frequency based on the selection on rocv_freq_sel. 0 = from latched fs[4:0] 1 = from the settings of rocv_f req_n[7:0] & ro cv_freq_m[6:0]. rocv_freq_n[7:0], rocv_freq_m[6:0] when rocv_freq_sel is set, the values programmed in rocv_freq_n[7:0] and rocv_freq_m[6:0] will be used to determine the recovery cp u output frequency when a watchdog timer time-out occurs. the setting of fs_overri de bit determines the frequency ratio for cpu, agp and pic. when it is cleared, the same frequency ra tio stated in the latched fs[4:0] register will be used. when it is set, the frequency ratio stated in the sel[4:0] register will be used. the new frequency will start to load whenever there is an update to either rocv_freq_n[7:0] and rocv_freq_m[6:0]. therefore, it is recommended to use word or blo ck write to update both registers within the same smbus bus operation. wd_en 0 = stop and reload watchdog timer. 1 = enable watchdog timer. it will start counting down after a frequency change occurs. wd_to_status watchdog timer time-out status bit 0 = no time-out occurs (read); ignore (write) 1 = time-out occurre d (read); clear wd_to_status (write). wd_timer[4:0] these bits store the time-out value of the watc hdog timer. the scale of the timer is determine by the prescaler. the timer can support a value of 150 ms to 4.8 sec when the pre-scaler is set to 150 ms. if the pre-scaler is set to 2.5 sec, it can support a va lue from 2.5 sec to 80 sec. when the watchdog timer reaches ?0,? it will set the wd_to_status bit. wd_pre_scaler 0 = 150 ms 1 = 2.5 sec rst_en_wd this bit will enable the generation of a reset pulse when a watchdog timer time-out occurs. 0 = disabled 1 = enabled rst_en_fc this bit will enable the generation of a reset pulse after a frequency change occurs. 0 = disabled 1 = enabled table 5. register summary (continued) . name description
cy28325-3 rev 1.0, november 21, 2006 page 14 of 18 table 6. examples of n and m value for different cpu frequency range frequency ranges gear constants fixed value for m-value register range of n-value register for different cpu frequency 50 mhz?129 mhz 48.00741 93 97 - 255 130 mhz?248 mhz 48.00741 45 127 - 245 absolute maximum conditions [2] parameter description condition min. max. unit v dd, v ddc, v dda, v ddx 3.3v supply voltage maximum functional voltage ?0.5 5.5 v v ddq analog supply voltage maximum functional voltage ?0.5 5.5 v v in input voltage relative to v ss ?0.5 v dd + 0.5 v t s temperature, storage non-functional ?65 150 c t a temperature, operating ambient functional 0 70 c t j temperature, junction functional 150 c esd hbm esd protection (human body model) mil-std-883, method 3015 2000 ? v ? jc dissipation, junction to case mil-spec 883e method 1012.1 31.03 c/w ? ja dissipation, junction to ambient jedec (jesd 51) 77.42 c/w ul?94 flammability rating at 1/8 in. v?0 msl moisture sensitivity level 1 operating conditions parameter description min. max. unit v dd_ref , v dd_pci ,v dd_agp, v dd_cpu, vdd_48mhz 3.3v supply voltages 3.135 3.465 v v dd_cppu_cs cpu_cs supply voltage 2.375 2.625 v c in input pin capacitance 5 pf c xtal xtal pin capacitance ? 22.5 pf c l max. capacitive load on 24_48mhz, 48 mhz, ref pci, agp ?20 30 pf f (ref) reference frequency, oscillator nominal value 14.318 14.318 mhz note: 2. multiple sequence: the voltage on any input or i/o pin cannot exceed the powe r pin during power-up. power suppl y sequencing is not required.
cy28325-3 rev 1.0, november 21, 2006 page 15 of 18 - dc electrical specifications parameter description test conditions min. max. unit v ih high-level input voltage except crystal pads. threshold voltage for crystal pads = v dd /2 2.4 ? v v il low-level input voltage except crystal pads ? 0.8 v v oh high-level output voltage 24_48mhz, 48 mhz, ref, agp i oh = ?1 ma 2.4 ? v pci i oh = ?1 ma 2.4 ? v v ol low-level output voltage 24_48mhz, 48 mhz, ref, agp i ol = 1 ma ? 0.4 v pci i ol = 1 ma ? 0.55 v i ih input high current 0 < v in < v dd ?5 5 a i il input low current 0 < v in < v dd, except inputs with pull-ups ?5 5 a i ipul input low current 0 < v in < v dd, inputs with pull-ups ?50 ? a i oh high-level output cu rrent cput0:1,cpuc0:1 for i oh =6*iref configuration type x1, v oh = 0.65v ?12.9 ? ma type x1, v oh = 0.74v ? ?14.9 ref, 24_48mhz, 48 mhz type 3, v oh = 1.00v ?29 ? type 3, v oh = 3.135v ? ?23 agp, pci type 5, v oh = 1.00v ?33 ? type 5, v oh = 3.135v ? ?33 i ol low-level output current ref, 24_48mhz, 48 mhz type 3, v ol = 1.95v 29 ? ma type 3, v ol = 0.4v ? 27 agp, pci type 5, v ol =1.95 v 30 ? type 5, v ol = 0.4v ? 38 i dd33 power supply current 3.3 v dd = 3.465v, ? 250 ma i dd25 power supply current 2.5 v dd = 2.625v ? 75 ma i ddpd shutdown current 3.3 v dd = 3.465v ? 20 ma ac electrical specifications [3] parameter output description test conditions min. max. unit t 1 24_48 mhz, 48 mhz, ref, pci output duty cycle [4] measured at 1.5v 40 60 % t 1 apic, agp output duty cycle [4] measured at 1.5v 35 65 % t 1 cput/c output duty cycle measured at v cross 45 55 % t 1 cput/c_cs output duty cycle measured at v cross 166mhz 45 55 % t 1 cput/c_cs output duty cycle measured at v cross @ 200mhz 30 70 % t 2 24_48 mhz, 48 mhz, pci, pci_f, ref, agp rising edge rate [6] between 0.8v and 2.0v 0.5 2.2 ns t 2 apic rising edge rate [6] between 0.8v and 2.0v 0.5 2.3 ns t 3 24_48 mhz, 48 mhz, pci, pci_f, ref, agp falling edge rate between 2.0v and 0.8v 0.5 2.2 ns t 3 apic falling edge rate [7] between 2.0v and 0.8v 0.5 2.3 ns t 5 agp[0:2] agp-agp skew measured at 1.5v ? 300 ps t 6 pci pci-pci skew measured at 1.5v ? 500 ps t 9 agp, apic cycle-cycle clock jitter measured at 1.5v t 9 = t 9a ? t 9b ?500ps t 9 24_48 mhz, 48 mhz cycle-cycle clock jitte r measured at 1.5v t 9 = t 9a ? t 9b ?350ps t 9 pci cycle-cycle clock jitte r measured at 1.5v t 9 = t 9a ? t 9b ?500ps
cy28325-3 rev 1.0, november 21, 2006 page 16 of 18 t 9 ref cycle-cycle clock jitte r measured at 1.5v t 9 = t 9a ? t 9b ? 1000 ps 0.7v cput/c, cpu_cs t 2 cpu rise time measured single ended waveform from 0.175v to 0.525v 0.175 1.6 ns t 3 cpu fall time measured single ended waveform from 0.525v to 0.175v 0.175 1.6 ns t 4 cpu cpu-cpu skew measured at crossover ? 150 ps t 8 cpu cycle-cycle clock jitter m easured at crossover t 8 = t 8a ? t 8b with all outputs running ?300ps cpu rise/fall matching measured with test loads [5, 6] ?20% v oh cpu high-level output voltage including overshoot measured with test loads [6] ?0.85 v v ol cpu low-level output voltage including undershoot measured with test loads [6] ?0.15 ? v v crossover cpu crossover voltage measured with test loads [6] 0.28 0.43 v ac electrical specifications [3] (continued) parameter output description test conditions min. max. unit switching waveforms notes: 3. all parameters specified with loaded outputs. 4. duty cycle is measured at 1.5v when v dd = 3.3v. when v dd = 2.5v, duty cycle is measure at 1.25v. 5. determined as a fraction of 2*(trp-trn)(trp+trn) where tr p is a rising edge and trp is an intersectiong falling edge. 6. the 0.7v test load is r s =33.2ohm, r p = 49.9ohm in test circuit. 7. characterize with control register, data byte 9, bits 5 and 6 = 1. duty cycle timing t 1b (single-ended output) t 1a duty cycle timing t 1b t 1a (cpu differential output) all outputs rise/fall time output t 2 v dd 0v t 3
cy28325-3 rev 1.0, november 21, 2006 page 17 of 18 switching waveforms (continued) cpu-cpu clock skew host_b host t 4 host_b host agp-agp clock skew agp agp t 5 pci-pci clock skew pci pci t 6 t 8a t 8b cpu clock cycle-cycle jitter host_b host t 9a t 9b cycle-cycle clock jitter clk ordering information ordering code package type operating range CY28325OC-3 48-pin shrunk small outline package (ssop) commercial, 0c to 70c CY28325OC-3t 48-pin shrunk small outline package (ssop) - tape and reel commercial, 0c to 70c cy28325oxc-3 48-pin shrunk small outline package (ssop)- lead free commercial, 0c to 70c cy28325oxc-3t 48-pin shrunk small outline package (ssop) - tape and reel- lead free commercial, 0c to 70c
rev 1.0, november 21, 2006 page 18 of 18 cy28325-3 while sli has reviewed all information herein for accuracy and re liability, spectra linear inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. this product i s intended for use in normal commercial applications and is not warranted nor is it inte nded for use in life support, critical medical instruments, o r any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursu ant to additional processing by spectra linear in c., and expressed written agreement by spectra linear inc. spectra linear inc. reserves the righ t to change any circuitry or specification without notice. package drawing and dimensions 48-lead shrunk small outline package o48

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